FIG. 1 depicts a block diagram of a multi-channel solid state drive (SSD) device 100. A typical multi-channel SSD device 100 includes a SSD controller 102, external (or internal) buffers 104, a host interconnect 105, a plurality of channels 107, 109, 111, 113 and 115, and flash memory devices 108, 110, 112, 114, and 117, each of which is connected to each of channels 107, 109, 111, 113, and 115, respectively. SSD controller 102 includes a host interface 116, a processor 118, and a flash controller 120. Host interface 116 connects SSD controller 102 to an external host through host interconnect 105. Processor 118 controls the operation of each component of SSD controller 102. Flash controller 120 controls communication between SSD controller 102 and each of the flash memory devices 108, 110, 112, 114 and 116, over channels 107, 109, 111, 113, and 115. Each flash memory device includes one or more circuit dies that are contained within a package.
FIG. 2 depicts a single-channel SSD device 200. Single-channel SSD device 200 has the same SSD controller 102 as multi-channel SSD device 100 shown in FIG. 1. However, instead of having a plurality of channels, single-channel SSD device 200 has one channel 210 that connects each of the flash memory devices 108, 110, 112, 114, and 116 to flash controller 120. Each flash memory device 108, 110, 112, 114, and 116 includes one or more circuit dies (shown as three dies in FIG. 2) that are contained within a package.
The number of channels in an SSD device is determined by a capacity target and/or power consumption of the controller. An important design consideration for such controllers is the number of channels. Controllers often use many channels to satisfy the throughput requirement and to connect as many flash devices as needed to reach the target drive capacity. The embodiments of FIGS. 1 and 2 are amenable to prior flash interface speeds, which are around 40 MT/s to 166 MT/s (million transfers per second). MT/s is a measurement of channel speed in millions of effective cycles per second. It is a rate at which the data is actually transferred, as opposed to the frequency of the clock that drives the flash interface.
In the past few years, flash interface speed has increased from 40 MT/s to about 400 MT/s (+/−10%.) Furthermore, interface speeds are expected to exceed 400 MT/s in next few years. In addition to speed increases, the size increase of SSDs (i.e., the number of flash memory devices and dies increases) also causes the performance of the current SSD device to deteriorate. For example, in a shared channel SSD, several flash devices share the same control and data channel to communicate with the controller. This means the load on the channel increases as the number of flash devices increase. The situation worsens as the number of dies within each flash device or the number of flash memory devices increases. This increase in the number of dies results in higher capacitive load per flash memory device. As an example, Table 1 shows the load for different packages that include two dies (dual die package (DDP)), four dies (quad die package (QDP)), and eight dies (octa die package (ODP)).
TABLE 1Capacitive load of a flash device with multiple die in packageDual ChannelDual ChannelDual Channel DDPQDPODP8 picofarads13 picofarads23 picofarads
Driving large capacitive loads is an issue for both the SSD controller and flash devices. When designing a SSD controller, one could design or use an input/output (I/O) with a higher capacitance drive capability. However, such a design would impact the flash side limiting the device to 16 flash dies per channel, for example. As the number of flash memory devices increases, the capacitive load on the channel increases. This in turn causes the signal quality to decrease. For example, FIG. 3 depicts a Data Eye Diagram (DQ) at 200 MHz operation for a 32-die shared channel device with output state logic power voltage (VCCQ) of 3.3V. Specifically, FIG. 3 shows the signal quality when a flash memory device sends data to a controller in a 32-die shared channel environment. As shown, the data eye window is not recognizable. Therefore, the SSD controller cannot latch the incoming data from flash. Thus, at 200 MT/s, a 32-die shared channel device is unworkable using current techniques.